Specifications

REV.-A
A.1.4
ER59256 (lC)
The ER59256 is a 256-bit nonvolatile CMOS
be transferred serially over the data bus.
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RAM containing 16 words x 16 bits, and the data can
The
ER59256 uses a compact and low-priced 8-pin package. Each bit of RAM is paired with a bit in
the nonvolatile electrically programmable ROM
(EEPROM) for backup. Data is transferred between the
RAM and
EEPROM upon receiving an instruction, STORE signal , or RECALL signal from the processor.
The nonvolatile data is stored in the
EEPROM. The data in the RAM is read/written independently of
the data stored in the
EEPROM. The ER59256 requires only a signal 5V power supply.
All inputs are
ITL level inputs.
n
CE 1
5 Vcc
CE
CHIP ENABLE
SK
SERIAL CLOCK
Sx
2
6
STORE
DI
SERIAL DATA IN
DO
SERIAL DATA OUT
DI 3
7
RECALL
RECALL
RECALL
STORE
STORE
DO 4
8
VSS
Vcc
+5V
I
I
Vss
GROUND
Figure A-9. ER59256 Pin Diagram
EEPROM
STORE
/ /r/i I
~
ROW
RECALL
DECODER
Stored RAM
STORE
CE
D
~
m
ERASE/WRITE
ERASE/WRITE
s?+— -
PROTECTION
PROTECTION
ii~
Instruction
Clock
Decoder Generator
[
]
+1
,
I
1
I
I
I
-b-+
I/
Figure A-1 O. ER59256 Block Diagram
A-1 O