Specifications
REV.-A
A.1.3
2(964C
SRAM (3D)
The
2064C
is an 8K-byte CMOS static RAM. The
2064C
has low power consumption, and its
input\ output level is compatible with the
TTL
ICS.
Figure A-7 shows the
2064C
pin diagram, and Figure
A-8 shows a block diagram for the
2064C
static RAM.
Features
Capacity of 8192 words X 8 bits
TTL compatible
1/0
Power supply +5 VDC
Functions
AO - Al 2 : Input address
WE
: Write enable
m
: Output enable
CSI,CS2
: Chip select
DO - D7 : Input/Output data
NC
: No connection
NcnvQQ
iE
A12
2
27=
A7 3
26
CS2
A6
4
25 A8
a
A37
d
A28
d
Al 9
AO1O
b
21AI0
F
20KI
19D7
1806
u
VSS14
D
1503
AO
Al
&2
A3
A4
[
:
A5
z
A6
~
Al
:
A8
?
A9
:
AIO
a
All
A12
“1
:
Memory Cell Array
9
:
512
:
o
512 X 16 X.2
i
=
$
!6
X8
4
ROW
Gale
1
!
CS1
(
)’- CSI.CS2
Control
,8
CS2 (
*
Log, c
I
E(
*
SK
Control
lnput(Qutp. f Buffe,
WE-(
*
Logic
—
!
00
01
02
03 04 05 06 07
Figure A-7.
2064C
Pin Diagram
Figure A-8.
2064C
SRAM
Block Diagram
Table A-7.
2064C
Truth Table
7
Csl
CS2
OE
WE
AO-A12
DATA 1/0
MODE
H
x
—
High impedance Wait
L
High impedance Wait
L H
x
L
Stable
Input data
Read
L
H
L
H
Stable Output data
Write
L
H H H
Stable
High impedance
Output disable
NOTES: 1. X = HIGH or LOW
2.- = HIGH, LOW or High impedance
A-9