Specifications

10
S1C33000 Core
■ MEMORY MAP AND TRAP TABLE
■ REGISTERS
■ INSTRUCTION SET
● Instruction Format and Operation
∗ The cycle lists the number of execution cycles assuming that the instructions are stored in the built-in ROM and access to the built-in RAM.
∗ Sample format: signX and immX = immediate data, %XX = register
Classification Instruction Sample format Operation Cycle
Relative jp, jrgt, jrge, jrlt, jrle, jrugt, jruge, jp sing8 Branches to PC + (sign8 × 2) 1,2 (branch)
branch jrult, jrule, jreq, jrne, call or 3 (call)
Relative jp.d, jrgt.d, jrge.d, jrlt.d, jrle.d, jp.d sing8 Branches to PC + (sign8 × 2) 1
delayed jrugt.d, jruge.d, jrult.d, jrule.d, Executes the next instruction before or 2 (call)
branch jreq.d, jrne.d, call.d branching.
Absolute call, jp, call.d, jp.d call %rb Branches to the address indicated 1 to 3
branch with %rb.
Special ret, ret.d, int imm2, reti, brk, retb Return, interrupt, etc. 3 to 10
branch
Logic and, or, xor, not and %rd, %rs %rd = %rd & %rs 1
operation and %rd, sign6 %rd = %rd & sign6
Arithmetic add, sub add %rd, %rs %rd = %rd + %rs 1
operation add %rd, imm6 %rd = %rd + imm6
add %sp, imm12 %sp = %sp + imm12
Area 18 External memory
Area 17 External memory
Area 16 External memory
Area 15 External memory
Area 14 External memory
Area 13 External memory
Area 12 External memory
Area 11 External memory
Area 10 External memory
Area 9 External memory
Area 8 External memory
Area 7 External memory
Area 6 External I/O
Area 5 External memory
Area 4 External memory
Area 3 On-chip ROM
Area 2 Reserved
Area 1 Internal I/O
Area 0 On-chip RAM
Memory Map Trap Table
Trap table start address
When booting from built-in ROM: 0x0080000
When booting from external memory: 0x0C00000
The trap table can be relocated using the trap table
base register TTBR (memory-mapped register) after
resetting the CPU.
Vectors will be fetched from the trap table for booting
and interrupts.
0xFFFFFFF
0x1000000
0x0C00000
0x0100000
0x0080000
0x0060000
0x0040000
0x0000000
Area size
64MB
64MB
32MB
32MB
16MB
16MB
8MB
8MB
4MB
4MB
2MB
2MB
1MB
1MB
1MB
512KB
128KB
128KB
256KB
Reserved
External maskable interrupt 215
:
External maskable interrupt 0
Software exception 3
:
Software exception 0
Reserved
NMI
Address error
Reserved
Zero division
Reserved
Reset
Address offset
1023
929
64
60
48
32–44
28
24
20
16
4–12
0
R15
R14
:
R1
R0
31 0
General-purpose registers (16)
PC
PSR
SP
ALR
AHR
Program counter
Processor status register
Stack pointer
Arithmetic operation low register
Arithmetic operation high register
31 0
Special registers (5)
(AHR, ALR: Option for Multiplication & Accumulation, Multiplication, and Division)