Specifications

9
PF881-03
S1C33000 Core
32-bit Single Chip Microcomputer
● 32-bit RISC Core
● High-code-efficient Instruction Set
● Multiplication and Accumulation Instruction
● High-speed Operation and Low Current Consumption
■ DESCRIPTION
The S1C33000 is a 32-bit RISC-type core CPU for the S1C33 Family microprocessors. The S1C33 Family will
be developed using this core as the main unit and implementing various peripheral circuits such as RAM, ROM,
DMA, A/D and D/A converters. The S1C33000 core has a high-code efficient instruction set, MAC (multiplication
and accumulation) instruction and features high-speed operation and low current consumption. It is suitable for
a wide range of embedded applications such as portable equipment, OA and FA equipment, digital signal
processing systems and various controllers.
■ FEATURES
● Processor type ................................................ Seiko Epson original 32-bit RISC core
● Operating frequency ....................................... DC to 60MHz (differs depending on the S1C33xxx model)
● Instruction set.................................................. 16-bit fixed code size
105 types of instructions with high linearity
Principle instructions can be executed in one cycle.
● Multiplication and accumulation instruction .... MAC instruction (16 bits × 16 bits + 64 bits → 64 bits)
Executable in two cycles per operation
● Register set ..................................................... Sixteen 32-bit general-purpose registers
Five 32-bit special registers
● Memory space ................................................ 28-bit (256MB) space
A linear space including code, data and I/O areas.
The memory space is divided into 19 areas and they can be
accessed with the select signals delivered from the core.
● Immediate data extension............................... Immediate data in the instruction codes can be extended up
to 32 bits using the EXT instruction.
● Interrupts ......................................................... Reset, NMI and 216 external interrupts
Four software exceptions and two instruction execution ex-
ceptions
The core fetches vectors in the trap table to branch process-
ing.
● Reset ............................................................... Cold reset (for resetting all conditions)
Hot reset (resetting except for bus and port status)
Trap table is selectable from internal or external memory
when booting and is relocatable.
● Power down mode ..........................................HALT instruction (stops the core only.)
SLP instruction (stops all the circuits.)
● Others ............................................................. Little endian/Big endian format
Harvard architecture