Specifications

Appendix i3
Printhead Drive Circuit
Figure B-9 shows the printhead drive circuit block diagram. The print data already
is expanded to create the image data. The CPU splits up this data three times and
transfers this information to the latch circuit within the head gate array (IC2).
The
CPU samples the voltage from the +35 V line via the ND converter. The CPU
outputs a pulse via P83, the CPU time output port. The length of this pulse
corresponds to the voltage of the +35 V line. This pulse becomes the head drive
signal. In this way, head gate array (IC21 outputs head drive signals (signals HDl
to HD24) that relate to voltage level through the width of the pulses. These signals
are output to the head for each of the section of print data that were created by
subdividing the data three times before sending.
By sampling the +35 V line voltage and determining the length of the head drive
signal, it is possible to maintain the energy supplied to the head at a constant level.
If the voltage of the +35 V line is HIGH, the CPU shortens the output pulse.
If the
voltage of the +35 V line is LOW, the CPU lengthens the output pulse.
-
TMP90CO41
E05A86
(IC21)
DO -D7
/
E05A50(ICll)
P83
- PP
/PPO
STA475
(W
DO -D7
HDl -24
PTS
(lob9)
4
Printhead
Figure B-9. Printhead Drive Circuit
B-14
Epson LQ-570+/1 070+