Specifications

Appendix B
Reset Circuit
Figure B-4 shows a block diagram for the reset circuit, which issues the /BESET
signal to initialize each part of the control circuit as it receives this signal. The
conditions when the /RESET signal is output are described below.
When Turning on the Power Supply
Immediately after power is turned on, PST 529 (IC19) outputs the /PON pulse.
The
E05A50 (ICll) receives this pulse and outputs the /DISC pulse. The electrical
charge in capacitor C29 is then discharged. Af%er this, the /THLD port within
E05A50 detects the low level and outputs the /RESET signal from the /OUT port of
IC19. After time has elapsed, the charge in the condenser builds up again. The
/THLD signal is canceled and then the /RESET signal is canceled.
Resets Performed by the CPU Itself (CPU Self-Reset)
The CPU outputs the /RESET signal if there is a /RESET request for E05A50 and
E05A50 output the /DISC pulse.
PST529(IC19) n
D2
EOS450(ICll)
R30
l l
/OUT
I”’ /PON
lo6 /THLD
105
/DISC
- -
D3
R31
““V
R32
Figure B-4. Reset Circuit Block Diagram
Epson LQ-570+/1 07o+
B-9