Specifications

REV.-A
2.3.7 Parallel Interface Circuit
Figure 2-26 shows the parallel interface circuit in block diagram form. The data sent from the host
computer is latched within E05A50 by the STROBE signal. E05A50 outputs the BUSY signal
automatically to stop the host computer from sending the next data and then outputs the IBF signal
for the CPU. The CPU receives the IBF signal via the interrupt signal input port P82, recognizes that
the data has been received from the host computer, and reads the data that was latched in the E05A50.
Next, the CPU resets the BUSY signal so that the printer is ready to receive more data from the host
computer.
Parallel I/F
DO-7
DINO-7 DATAO-7 - DO-7
STB ii%
STROBE - e .__-r-----------
I
I
I
I
BUSY + ----:
BUSY
P82
E05A50 (4D)
CPU (1C)
Figure 2-26. Parallel Interface Circuit
2.3.7 EEPROM Control Circuit
Figure 2-27 shows the EEPROM control circuit in block diagram form. The EEPROM is used to hold such
information as the top-of-form position. EEPROM is non-volatile memory and information is not lost when
the printer is powered off. Since the EEPROM is a serial I/O type device, the g-bit parallel data received
from the CPU is converted to serial data by the E05A50.
SCL -
SDA
i
EEPROM (4C)
DATA BUS
SCK
SDA
CPU (1C)
IE05A50 (4D)] 1
Figure 2-27. EEPROM Control Circuit
2-20