Computer Hardware User Manual
1: Introduction
ARM720T CORE CPU MANUAL EPSON 1-3
The functional signals on the ARM720T processor are shown in Figure 1-2.
Figure 1-2 ARM720T processor functional signals
1.1.1 EmbeddedICE-RT logic
The EmbeddedICE-RT logic provides integrated on-chip debug support for the ARM720T core.
It enables you to program the conditions under which a breakpoint or watchpoint can occur.
The EmbeddedICE-RT logic is an enhanced implementation of EmbeddedICE, and enables
you to perform debugging in monitor mode. In monitor mode, the core takes an exception on a
breakpoint or watchpoint, rather than entering debug state as it does in halt mode.
If the core does not enter debug state when it encounters a watchpoint or breakpoint, it can
continue to service hardware interrupt requests as normal. Debugging in monitor mode is
useful if the core forms part of the feedback loop of a mechanical system, where stopping the
core can potentially lead to system failure.
The EmbeddedICE-RT logic contains a
Debug Communications Channel
(DCC). The DCC is
used to pass information between the target and the host debugger. The EmbeddedICE-RT
logic is controlled through the
Joint Test Action Group
(JTAG) test access port.
ARM720T processor
HADDR[31:0]
EXT CPDBE
CPnM REQ
CPnTRANS
CPTBIT
CPnOPC
CPnCPI
EXT C PB
EXT C PA
EXTCPDOUT[31:0]
EXT C PDI N[ 31:0]
EXTCPCLKEN
HRESETn
HCLKEN
HLOCK
HBUSREQ
HRDATA[31:0]
HWDA T A[31:0]
HCLK
HRESP[1:0]
HREA DY
HGRANT
HPROT [ 3:0]
HSIZ E[ 2:0]
HWRITE
HBURST [ 2:0]
HTRANS[ 1:0]
DBGBREA K
DBGRNG[1:0]
DBGEXT [1:0]
DBGRQ
DBGEN
DBGACK
COMMTX
COMMRX
nFIQ
BIGENDOUT
VINITHI
nIRQ
DBGCAPT URE
DBGTAPSM [ 3:0]
DBGSDOUT
DBGSDIN
DBGSREG[3:0]
DBGIR[3:0]
DBGSHIFT
DBGUPDAT E
DBGnT DOEN
DBGEXT EST
DBGINT EST
DBGTM S
DBGTDO
DBGTDI
DBGTCKEN
DBGnT RST
ET M C PB
ET M C PA
ET M ABORT
ET M W DA T A[ 3 1 :0 ]
ET M RDAT A [ 31:0]
ET M DBGACK
ET M S I Z E[ 1:0 ]
ET M C L KEN
ET M n RW
ET M ADDR[ 31:0]
ET M n C P I
ETMINSTRVALID
ET M n EXEC
ET M S EQ
ET M n OP C
ET M n M REQ
ET M HI V EC S
ET M BI GEND
ET M EN
ET M T BI T
ET M PROC ID[31:0]
ET M PROC IDWR
SCANIN0 - SCANIN6
SCANOUT0 - SCANOUT6
TESTENABLE
SCANENABLE
AMBA
interf ac e
Coprocessor
interf ac e
Debug
interf ac e
Miscellaneous
signals
ATPG
Signals
JTAG
interf ac e
ETM interface
ATPG
Signals