User`s manual

The addresses for the page register are as below.

Table 6-10: I/O Hex Address

Address generation for the DMA channels is as below.

Table 6-11: DMA Channel 3 Through 0

Note: To generate the addressing signal “byte high enable” (BHE),

invert address line A0.

Table 6-12: DMA Channels 7 Through 5

Note: The BHE and A0 addressing signals are forced to a logical 0.

DMA channel addresses do not increase or decrease through page

boundaries 64KB for channels 0 through 3 and 128KB for channels 5

through 7).

Chapter 6: Appendix