User`s manual

Table 6-7: Channel 2
The 8254-2 timer/counter is treated by system programs as an arran-
gement of four programmable external I/O ports. Three are treated as
counters; the fourth is a control register for mode programming.
System Interrupts
Sixteen levels of system interrupts are provided by the 80286 NMI and
two 8259A interrupt controller chips. The following shows the interrupt-
level assignments in decreasing priority.
Level
Microprocessor NMI
Interrupt Controllers
CTLR1
IRQ0
IRQ 1
IRQ2
IRQ3
IRQ 4
IRQ5
IRQ6
IRQ7
CTLR2
IRQ8
IRQ9
IRQ 10
IRQ 11
IRQ 12
IRQ 13
IRQ 14
IRQ 15
Function
Parity or I/O Channel Check
Timer Output 0
Keyboard (Output Buffer Full)
Interrupt from CTLR 2
Realtime Clock Interrupt
Software Redirected to INT OAH (IRQ2)
Reserved
Reserved
Reserved
Coprocessor
Fixed Disk Controller
Reserved
Serial Port 2
Serial Port 1
Parallel Port 2
Diskette Controller
Parallel Port 1
Table 6-8: Interrupts Level Assignment
Chapter 6: Appendix 19