Specifications

ManualsBrandsEpson ManualsPrint & Scan570e - LQ B/W Dot-matrix Printer

REV.-A

2.3.6 Printhead Drive Circuit

‘\

Figure 2-24 shows the

printhead

drive circuit block diagram. The print data already is expanded to

create the image data. The CPU splits up this data three times and transfers this information to the

latch circuit within the Head Gate

Array(lC2). The CPU samples the voltage of the +35 V line via the

A/D

convertor (see Section 2.3.3). The CPU outputs a pulse via the CPU time output

pori

P63. The

length of this pulse corresponds to the

voftage

of the

+35

V line. This pulse becomes the head drive

signal. In this way, Head Gate

Array(iC2)

outputs head drive signals (signals

HD1

HD24)

that relate

to voltage level through the width of the pulses. These signals are output to the head for each of the

section of print data that were created by subdividing the data three times before sending.

By sampling the

+35 V line voltage and determining the length of the head drive signal, it is possible

to maintain the energy supplied to the head at a

mnstant

level. If the voltage of the

+35

V line is .

HIGH, the CPU shortens the output pulse. If the

voftage

of the +35 V line is LOW, the CPU lengthen

the output pulse.

TMP90C041

E05A86

(IC21)

(IC2)

-D7

E05A50(IC11)

HD1

-24

‘“npp

‘Pp”rrs

STA475

(IC4-9)

Printhead

Figure 2-24.

Printhead

Drive Circuit

2-19