Service manual
2.3.5 PF Motor Driver Circuit
The figure below shows the PF motor driver circuit.
The gate array receives phase data from the CPU via ports 7 (PPG3), 8 (PPG2), 9 (PPG1), and 10 (PPG0),
converts the data to TEA3718SDP form, and then sends that phase data via ports 32 (PHASEA) and ports 129
(PHASEB) to each ports 8 (PHASE) of TEA3718SDP. The PF driver current is controlled on the Gate Array
and the signals are output via port 62 (PFI0A), port 63 (PFI1A), port 64 (PFI0B), port 65 (PFI1B). These
controlled drive currents are output to the each ports 9 (IN0), port 7 (IN1)of the TEA3718SDP.
2.3.6 EEPROM Control Circuit
The EEPROM is non-volatile memory that stores information even if the printer power is off. The figure
below shows the EEPROM control circuit.
The EEPROM is controlled by CPU ports 9 (P70), 10 (P71), 11 (P72), and 12 (P73). Port 11 is the data
output line used to save the information to the EEPROM, and port 12 is the data input line used to read the
saved data from the EEPROM. Port 70 is the chip select line, and port 71 is the clock timing line. When the
PWDN signal (power down) is detected on port 20 (INTO), the CPU writes the necessary data to the
EEPROM before the +5 V line drops to 4.75 V.
CPU
P70
P71
P72
P73
CS
CK
DI
DO
EEPROM
9
10
11
12
1
2
3
4
IC 8
Figure 2-37 EEPROM Control Circuit
Gate
Array
PFI0A
PFI1A
IC11
OUTA
OUTB
15
1
VS1
VS2
GND1
GND2
GND3
GND4
+35V
C26
PF A
PF-A
3
+35
D5
D4
C67
1
C66
IN0
IN1
PHASE
IC14
OUTA
OUTB
15
1
VS1
VS2
GND1
GND2
GND3
GND4
PF B
PF-B
C67
C66
IN0
IN1
PHASE
2
4
D7
D6
+35
C73
PFI1B
PFI0B
PFFASEA
PFFASEB
PFHOLD
REF
REF
9
7
8
11
9
7
8
11
129
32
62
63
66
65
64
3
14
3
14
IC2
PG
13
PG
12
PG
11
PG
10
PP
G3
PP
G2
PP
G1
PP
G0
7
89
10
5
67
8
CPU
IC1
Figure 2-36 PF Motor Driver Circuit
Operation Principles LQ-2070 Servcie Manual
2-26 Rev.A