Specifications

BIOS EP-MVP4G
Page 4-8
4-3 Chipset Features Setup
Choose the “CHIPSET FEATURES SETUP” in the CMOS SETUP UTILITY menu
to display following menu.
Figure 4: Chipset Features Setup
Bank 0/1, 2/3, 4/5 DRAM Timing: This value in this field is set by the system
board manufacturer, depending on whether the board has paged DRAMs or EDO
(extended data output) DRAMs.
The Choice: Bank 0/1, 2/3, 4/5.
SDRAM Cycle length: This setting defines the CAS timing parameter of the
SDRAM in terms of clocks.
The default is 3.
2: Provides faster memory performance.
3: Provides better memory compatibility.
DRAM Read Pipeline: You may select Enabled fo this field when PBSRAMs are
installed. Pipelining improves system performance.
The Choice: Enabled, Disabled.
ROM PCI/ISA BIOS(2A5LHPA9)
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
Bank 0/1 DRAM Timing : SDRAM Fast OnChip USB : Enabled
Bank 2/3 DRAM Timing : SDRAM Fast USB Keyboard Support : Disabled
Bank 4/5 DRAM Timing : SDRAM Fast OnChip AGP : Enabled
SDRAM Cycle length : 3 OnChip Sound : Enabled
DRAM Page-Mode : Enabled
DRAM Fast Decoding : Disabled
DRAM Read Pipeline : Disabled
Sustained 3T Write : Enabled
Cache R/CPU W Pipeline : Enabled
Cache Timing : Fastest
Video BIOS Cacheabled : Enabled
System BIOS Cacheabed : Disabled
Memory Hole : Disabled
Init Display First : PCI Slot
Frame Buffer Size : 8M
AGP Aperture Size : 64M
Esc : Quit : Select Item
F1 : Help PU/PD/+/- : Modify
F5 : Old Values (Shift) F2 : Color
F7 : Load Setup Defaults
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