Operation Manual
BIOS
Page 4-11
PCI Master 0 WS Write: When Enabled, writes to the PCI bus are command with
zero wait states.
The Choice: Enabled, Disabled.
PCI Delay Transaction: The chipset has an embedded 32-bit posted write buffer
to support delay transactions cycles. Select Enabled to support compliance with
PCI specification version 2.1.
The Choice: Enabled, Disabled.
PCI #2 Access #1 Retry: This item allows you enabled/disable the PCI #2
Access #1 Retry.
The Choice: Enabled, Disabled.
AGP Master 1 WS Write: When Enabled, writes to the AGP (Accelerated
Graphics Port) are executed with one wait states.
The Choice: Enabled, Disabled.
AGP Master 1 WS Read: When Enabled, read to the AGP (Accelerated Graph-
ics Port) are executed with one wait states.
The Choice: Enabled, Disabled.










