Specifications

BIOS EP-MVP3G-M/2/5
Page 4-8
Bank 0/1, 2/3, 4/5 DRAM Timing: This value in this field is set by the system
board manufacturer, depending on whether the board has paged DRAMs or EDO
(extended data output) DRAMs.
The Choice: Bank 0/1, 2/3, 4/5.
SDRAM Cycle length: This setting defines the CAS timing parameter of the
SDRAM in terms of clocks. The default is 3.
2: Provides faster memory performance.
3: Provides better memory compatibility.
SDRAM Bank Interleave: The default value is Disabled.
Disabled : Normal Setting.
2 Bank/4 Bank: SDRAM 2 or 4 Bank Interleave.
DRAM Page-Mode: The item will active or inactive chipset page registers.
Enabled: Page-Mode Enabled.
Disabled: No page registers update and non Page-Mode operation.
DRAM Fast Decoding: The item will effective DRAM operation sequential.
Video BIOS Cacheable: This option copies the video ROM BIOS to fast RAM
(C0000h to C7FFFh). The default is Enabled.
Enabled: Enables the Video BIOS Cacheable to speed up the VGA Performance.
Disabled: Will not use the Video BIOS Cacheable function.
System BIOS Cacheable: This allows you to copy your BIOS code from slow
ROM to fast RAM. The default is Disabled.
Enabled: The option will improve system performance. However, if any pro-
gram writes to this memory area, a system error may result.
Disabled: System BIOS non-cacheable.
Memory Hole at 15M-16M Addr.: The default value is Disabled.
Disabled: Normal Setting.
Enabled : This field enableds the main memory (15~16MB) remap to ISA BUS.
AGP Aperture Size: The amount of the system memory that the AGP card is
allowed to share. The options available are 4M, 8M, 16M, 32M, 64M, 128M,
256M. The default value is 64M.