Specifications

Computer Architecture and Maintenance (G-Scheme-2014)

DDR3 SDRAM

DDR3 continues the trend, doubling the minimum read or write unit to 8 consecutive

words. This allows another doubling of bandwidth and external bus rate without

having to change the clock rate of internal operations, just the width. To maintain 800–

1600 M transfers/s (both edges of a 400–800 MHz clock), the internal RAM array has to

perform 100–200 M fetches per second.

Again, with every doubling, the downside is the increased latency. As with all DDR

SDRAM generations, commands are still restricted to one clock edge and command

latencies are given in terms of clock cycles, which are half the speed of the usually

quoted transfer rate (a CAS latency of 8 with DDR3-800 is 8/(400 MHz) = 20 ns, exactly

the same latency of CAS2 on PC100 SDR SDRAM).

DDR3 memory chips are being made commercially, and computer systems using them

were available from the second half of 2007, with significant usage from 2008 onwards.

Initial clock rates were 400 and 533 MHz, which are described as DDR3-800 and DDR3-

1066 (PC3-6400 and PC3-8500 modules), but 667 and 800 MHz, described as DDR3-1333

and DDR3-1600 (PC3-10600 and PC3-12800 modules) are now common

Features of DDR-3

i. New Pin ie asynchronous RESET pin was introduced

ii. On-DIMM mirror friendly DRAM pin out

iii. Read and Write calibration

iv. Operating voltage 1.5V

v. Prefetch 8bit at a time

vi. Speed- 800Mhz , 1066Mhz , 1333Mhz , 1600Mhx and Above

DDR4 SDRAM

DDR4 SDRAM is the successor to DDR3 SDRAM. It was revealed at the Intel

Developer Forum in San Francisco in 2008, and is due to be released to market during

2011. The timing has varied considerably during its development - it was originally

expected to be released in 2012, and later (during 2010) expected to be released in 2015,

before samples were announced in early 2011 and manufacturers began to announce

that commercial production and release to market was anticipated in 2012. DDR4 is

expected to reach mass market adoption around 2015, which is comparable with the

approximately 5 years taken for DDR3 to achieve mass market transition over DDR2.

Prepared By – Prof. Manoj.kavedia (9860174297 – 9324258878 ) (www.kavediasir.yolasite.com)