Specifications

Computer Architecture and Maintenance (G-Scheme-2014)
Process technologies
Q.List and explain different Process technologies
Ans. 1. Dual Independent Bus Architecture
2. Hyper threading
3.MutliCore
Dual Independent Bus – Architecture
The Dual Independent Bus (DIB) architecture was first implemented in the sixth-
generation processors from Intel and AMD. DIB was created to improve processor bus
bandwidth and performance. Having two (dual) independent data I/O buses enables
the processor to access data from either of its buses simultaneously and in parallel,
rather than in a singular sequential manner (as in a single-bus system). The main (often
called front-side) processor bus is the interface between the processor and the
motherboard or chipset. The second (back-side) bus in a processor with DIB is used for
the L2 cache, enabling it to run at much greater speeds than if it were to share the main
processor bus.
Two buses make up the DIB architecture: the L2 cache bus and the main CPU
bus, often called FSB (front side bus). The P6 class processors, from the Pentium Pro to
the Core 2, as well as Athlon 64 processors can use both buses simultaneously,
eliminating a bottleneck there. The dual bus architecture enables the L2 cache of the
newer processors to run at full speed inside the processor core on an independent bus,
leaving the main CPU bus (FSB) to handle normal data flowing in and out of the chip.
The two buses run at different speeds. The front-side bus or main CPU bus is coupled
to the speed of the motherboard, whereas the back-side or L2 cache bus is coupled to
the speed of the processor
core. As the frequency of
processors increases, so
does the speed of the L2
cache.
DIB also enables the
system bus to perform
multiple simultaneous
transactions (instead of
singular sequential
transactions), accelerating
the flow of information
within the system and
Prepared By – Prof. Manoj.kavedia (9860174297 – 9324258878 ) (www.kavediasir.yolasite.com)
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