User guide

24-19
SystemVerilog Testbench Constructs
time there are other important differences in a final block. A final
block is like a user-defined function call in that it executes in zero
simulation time and cannot contain the following:
• delay specifications
• event controls
• nonblocking assignment statements
• wait statements
• user-defined task enabling statements when the user-defined
task contains delay specifications, event controls, wait
statements, or nonblocking assignment statements
Multiple Program Support
The Multiple program block is Limited Customer availability (LCA)
feature in NTB (SV) and requires a separate license. Please contact
your Synopsys AC for a license key.
Multiple programs support enables multiple testbenches to run in
parallel. Use this when testbenches model standalone components
for example, Verification IP (or work from a previous project). Because
components are independent, direct communication between them
except through signals is undesirable. For example, a UART and CPU
model would communicate only through their respective interfaces,
and not through the testbench. Thus, multiple programs modeling
standalone components allows usage without having knowledge of
the code given, or requiring modifications to your own testbench