User guide

24-18
SystemVerilog Testbench Constructs
Final Blocks
The final block is Limited Customer availability (LCA) feature in NTB
(SV) and requires a separate license. Please contact your Synopsys
AC for a license key.
A final block executes in the last simulation time step. The following
example contains a final block:
`timescale 1ns/1ns
module test;
logic l1, l2;
initial
begin
#10 l1=0;
#10 l1=1;
#10 l1=0;
#10 l1=1;
#10 $finish;
end
always @ (posedge l1)
$display("l1 = %0b at %0t",l1,$time);
final $display(" simulation ends at %0t",$time);
endmodule
The $display system tasks display the following:
l1 = 1 at 20
l1 = 1 at 40
simulation ends at 50
The final block executes in the last simulation time step at time 50.
A final block is the opposite of an initial block in that an initial block
begins execution in the first simulation time step and a final block
executes in the last simulation time step. Apart from the execution