User guide

24-16
SystemVerilog Testbench Constructs
Program blocks begin with the keyword program, followed by a name
for the program, followed by an optional port connection list, followed
by a semi colon (;). Program blocks end with the keyword
endprogram, for example:
program prog (input clk,output logic [31:0] data, output
logic ctrl);
logic dynamic_array [];
logic assoc_array[*];
int intqueue [$] = {1,2,3};
class classA;
function void vfunc(input in1, output out1);
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endfunction
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endclass
semaphore sem1 =new (2);
mailbox mbx1 = new();
reg [7:0] reg1;
covergroup cg1 @(posedge clk);
cp1: coverpoint reg1;
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endgroup
endprogram
bit clk = 0;
logic [31:0] data;
logic ctrl;
module clkmod;
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