User guide

24-3
SystemVerilog Testbench Constructs
Runtime Options
There are runtime options that were developed for OpenVera
testbenches that also work with SystemVerilog testbenches.
+ntb_random_seed=integer
Sets the seed value used by the top level random number
generator at the start of simulation. This option does not work for
the Verilog $random(seed) system function.
+ntb_solver_mode=1|2
Specifies the constraint solver mode for the randomize()
method:
1
The solver spends more pre-processing time in analyzing the
constraints, during the first call to randomize() on each class.
Subsequent calls to randomize() on that class are very fast.
2
The solver does minimal pre-processing, and analyzes the
constraint in each call to randomize(). Default is 2.
The randomize() method is described in “Randomize Methods”
on page 24-100.
+ntb_enable_solver_trace=0|1|2
Specifies the debugging mode when VCS executes the
randomize() method:
0
Disables tracing.
1
Enables tracing. This is the default.