User guide

24-2
SystemVerilog Testbench Constructs
vcs -sverilog -ntb_opts options <SV source code files>
As the use of vcs indicates, SystemVerilog files are treated like
Verilog files in the VCS flow. You can also specify other NTB options:
For example:
vcs -sverilog tb.sv
or
vcs -sverilog -f tb.list
Options For Compiling and Simulating SystemVerilog
Testbench Constructs
Compile-Time Options
The following compile-time options, used for both Verilog and
SystemVerilog code have been tested with SystemVerilog testbench
code:
-f filename
+define+macro_name=value
+incdir+directory_name
+libext+ext
-y directory_name
-timescale=time_unit/time_precision