User guide

24-1
SystemVerilog Testbench Constructs
24
SystemVerilog Testbench Constructs 1
The new version of VCS has implemented some of the SystemVerilog
testbench constructs. As testbench constructs they must be in a
program block (see “Program Blocks” on page 24-15).
Enabling Use of SystemVerilog Testbench Constructs
You enable the use of SystemVerilog testbench constructs with the
-sverilog compile-time option.
VCS Flow for SVTB
The VCS use model now includes the use model for SystemVerilog
NTB. The most important part is analyzing the SystemVerilog source
code You can do this as follows: