User guide

23-66
SystemVerilog Assertion Constructs
In this example simulation, signal clk initializes to 0 and toggles every
1 ns, so the clock ticks at 1 ns, 3 ns, 5 ns and so on.
A typical display of this system task is as follows:
Assertion test.a1 [’design.v’27]:
5ns: tracing "test.a1" started at 5ns:
attempt startingfound: req1looking for: req2 or
any
5ns: tracing "test.a1" started at 3ns:
trace: req1 ##1 anylooking for: req2 or any
failed: req1 ##1 req2
5ns: tracing "test.a1" started at 1ns:
trace: req1 ##1 any[* 2 ]looking for: req2 or any
failed: req1 ##1 any ##1 req2
Breaking this display into smaller chunks:
Assertion test.a1 [’design.v’27]:
The display is about the assertion with the hierarchical name test.a1.
It is in the source file named design.v and declared on line 27.
5ns: tracing "test.a1" started at 5ns:
attempt startingfound: req1looking for: req2 or
any