User guide

23-65
SystemVerilog Assertion Constructs
Here:
0
Specifies reporting on the assertion if it is active (VCS is checking
for its properties) and for the rest of the simulation reporting on
the assertion or assertions, whenever they start.
1
Specifies reporting on the assertion or assertions only once, the
next time they start.
If you specify neither 0 or 1, the default is 0.
assertion_identifier...
A comma separated list of assertions. If one of these assertions
is not declared in the module definition containing this system
task, specify it by its hierarchical name.
Consider the following assertion:
property p1;
@ (posedge clk) (req1 ##[1:5] req2);
endproperty
a1: assert property(p1);
For property p1 in assertion a1, a clock tick is a rising edge on signal
clk. When there is a clock tick VCS checks to see if signal req1 is
true, and then to see if signal req2 is true at any of the next five clock
ticks.