User guide

23-64
SystemVerilog Assertion Constructs
Each number is a hypertext link that takes you to a list of each type
of statement, directive, or event. For assert statements or
directives, the list shows you the number of attempts, successes,
failures, and incompletes. For cover statements or directives and
events, the list shows you the number of attempts, all matches, first
matches, and incompletes.
Assertion Monitoring System Tasks
For monitoring SystemVerilog assertions we have developed the
following new system tasks:
$assert_monitor
$assert_monitor_off
$assert_monitor_on
Note:
Enter these system tasks in an initial block. Do not enter these
system tasks in an always block.
The $assert_monitor system task is analogous to the standard
$monitor system task in that it continually monitors specified
assertions and displays what is happening with them (you can have
it only display on the next clock of the assertion). Its syntax is as
follows:
$assert_monitor([0|1,]assertion_identifier...);