User guide

23-61
SystemVerilog Assertion Constructs
This information is the total number and percentage of
SystemVerilog cover statements with sequences with all
matches.
Cover Directive for Sequence with First Matches
Total number and percentage of SystemVerilog cover
statements where the argument is a sequence, and there was a
cycle delay range expression, and the first possible match for the
sequence occurred.
Total number of Events
In OpenVera assertions, you can define a sequential expression
as an event. This information is the total number of such events.
Events Not Covered
Total number and percentage of OpenVera events that did not
occur (not covered).
Events with at least 1 real Match
Total number and percentage of OpenVera events that occurred
(were covered).
Events without any match or with only vacuous match
Total number and percentage of OpenVera events for which there
was no match or only a vacuous match.
Events without any Attempts
Total number and percentage of OpenVera events for which there
were no attempts.
At the bottom of the file are hypertext links to the other files written
by assertCovReport:
• Lists of tests merged to generate this report (tests.html)
• Hierarchical coverage report (hier.html)
• Category based coverage report (category.html)