User guide

23-60
SystemVerilog Assertion Constructs
Total number of Cover Directives for Sequences
A SystemVerilog cover statement can have a sequence name
for an argument instead of a property. For example:
sequence s8;
@(posedge clk1) sig17 ##[1:5] sig18;
endsequence
c7: cover property (s8);
or
sequence s8;
sig17 ##[1:5] sig18;
endsequence
c7: cover property (@(posedge clk1) s8);
This information is the total number of such cover statements.
Cover Directive for Sequence not Covered
Total number and percentage of SystemVerilog cover
statements, where the argument is a sequence that did not occur
during simulation.
Cover Directive for Sequence with All Matches
If there is a cycle delay range expression in a sequence. For
example:
sequence s1;
@(posedge clk1) sig1 ##[1:5] sig2;
endsequence
After sig1 is true, there could be a match after one, two, three,
four, or five rising edges on clk1, if sig2 is also true. If all these
matches happen for all attempts, then this is a sequence of all
matches.