User guide

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SystemVerilog Assertion Constructs
Cover Directive for Property Not Covered
The total number and percentage of SystemVerilog assertion
cover statements with the name of a property is their argument,
where the design’s behavior never matches the property specified
in the cover statement.
Cover Directive for Property with Matches
The total number and percentage of SystemVerilog assertion
cover statements with the name of a property as their argument,
where the design’s behavior, at least some of the simulation time,
matches the property specified in the cover statement.
Cover Directive for Property with Vacuous Matches
A property for a SystemVerilog cover statement automatically
matches if there is an implication for the property and the
antecedent condition is never true. For example:
sequence s5;
sig11 ##1 sig12;
endsequence
property p5;
@(posedge clk1) (sig9 ##1 sig10) |-> s5;
endproperty
c4: cover property (p5);
If the antecedent (sig9 ##1 sig10) never occurs, property p5
matches, even if the consequent sequential expression
sig11 ##1
sig12 never occurs. This is why such a match is vacuous or empty.
This information is the total number and percentage of
SystemVerilog assertion cover statements with the name of a
property as their argument, and the total number of OpenVera
cover directives, where there is a vacuous match.