User guide

23-58
SystemVerilog Assertion Constructs
Assertions with at least 1 Real Success
SystemVerilog and OpenVera assertions can fail at certain times
during simulation and succeed at other times. This is the total
number and percentage of SystemVerilog and OpenVera
assertions that had at least one success during simulation.
Assertions with at least 1 Failure
The total number an percentage of SystemVerilog and OpenVera
assertions that had a least one failure during simulation.
Assertions with at least 1 Incomplete
Assertions specify a property about the design that can occur over
a span of simulation time. This is the total number and percentage
of assertions that VCS began to monitor, but simulation ended
before the design matched the behavior specified in the assertion.
Assertions without Attempts
VCS looks to see if the design matches the behavior in the
assertion when there is a transition on a clock signal for the
property (you can specify the type of transition). If none of these
clock signal transitions occur, then there is no attempt at the
assertion. This is the total number and percentage of assertions
with no attempts.
Total number of Cover Directives for Properties
The argument to a SystemVerilog assertion cover statement can
be the name of a defined and declared property (between the
property and endproperty keywords) or the argument can
be just the building blocks of a property between parentheses (a
clock signal and a sequential expression).
This value is the total number of SystemVerilog assertions cover
statements with the name of a property as their argument.