User guide

23-55
SystemVerilog Assertion Constructs
6vacuoussuccess
Holds the count of vacuous successes.
8incompletes
Holds the count of unterminated attempts
For SVA sequence coverage
1attempts
Holds the count of attempts.
3allsuccess
Holds the count of succesful attempts.
7firstmatches
Holds the count of generated .matched events.
8incompletes
Holds the count of unterminated attempts.
For OVA assertions
1attempts
Holds the count of attempts.
2failures
Holds the count of failed attempts.
3allsuccess
Holds the count of succesful attempts.
4realsuccess
Holds the count of attempts with nonvacuous success.
8incompletes
Holds the count of unterminated attempts.
For OVA events
1attempts
Holds the count of attempts.