User guide

23-44
SystemVerilog Assertion Constructs
Options for SystemVerilog Assertion Coverage
SystemVerilog assertion coverage monitors the design for when
assertions are met and not met. Coverage results are on assertions,
not the properties or sequences that might be instantiated in these
assertions. See "Reporting On Assertions Coverage" on page 23-45
To enable and control assertion coverage, VCS has the following
compile-time options:
-cm assert
Compiles for SystemVerilog assertions coverage. -cm is not a
new compile-time option but the assert argument is new. This
option and argument must also be entered at runtime.
-cm_assert_hier filename
Limits assertion coverage to the module instances specified in
filename. Specify the instances using the same format as VCS
coverage metrics. If this option is not used, coverage is
implemented on the whole design.
There are also the following runtime options for assertion coverage:
-cm assert
Specifies monitoring for SystemVerilog assertions coverage.
Like at compile-time, -cm is not a new runtime option but the
assert argument is new.
-cm_assert_name path/filename
Specifies the path and filename of an initial coverage file. An initial
coverage file is needed to set up the database. By default, an
empty coverage file is loaded from the following directory:
simv.vdb/snps/fcov.