User guide

23-43
SystemVerilog Assertion Constructs
@(posedge clk) sig1 && sig2 => s2;
endproperty
a1: assert property (p1);
a2: assert property (@(posedge clk)s1);
c1: cover property (p1);
c2: cover property (@(posedge clk)s1);
*/
The sv_pragma keyword must immediately follow the characters
that begin the comment: // for single line comments and /* for
multi-line comments.
Note:
This feature is intended allow SVA code as pragmas. When you
include the -sv_pragma compile-time option, VCS compiles all
the contents in the comment, not just the SVA code in the
comment. If the multi-line comment is the following:
/* sv_pragma
a1: assert property (p1);
a2: assert property (@(posedge clk)s1);
c1: cover property (p1);
c2: cover property (@(posedge clk)s1);
initial
$display("$display with SVAs");
*/
VCS displays the $display with SVAs character string at
runtime.