User guide

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SystemVerilog Assertion Constructs
Disabling SystemVerilog Assertions at Compile-Time
You can specify a list of SystemVerilog assertions in your code that
you want to disable at compile-time. You do so with the -assert
compile-time option and disable_file=filename argument, for
example:
vcs -sverilog -assert disable_file=disable_assertions.txt
Enter one absolute hierarchical name of a SystemVerilog assertion
on each line, for example:
test.dev1.a1
Only one hierachical assertion name to a line.
Entering SystemVerilog Assertions as Pragmas
If your code has to be read by a tool that has not implemented
SystemVerilog Assertions, you can enter your SVA code as pragmas
(or metacomments) so that the other tool ignores the SVA code. You
can tell VCS to compile the SVA code by including the -sv_pragma
compile-time option. The following is an example of SVA code as
pragmas:
// sv_pragma sequence s1;
// sv_pragma @(posedge clk) sig1 ##[1:3] sig2;
// sv_pragma endsequence
/* sv_pragma
sequence s2;
sig3 ##[1:3] sig4;
endsequence
property p1;