User guide

2-25
Modeling Your Design
Memory Size Limits in VCS
The bit width for a word or an element in a memory in VCS must be
less than 0x100000 (or 2
20
or 1,048,576) bits.
The number of elements or words (sometimes also called rows) in a
memory in VCS must be less than 0x3FFF_FFFE-1 (or 2
30
- 2 or
1,073,741,822) elements or words.
The total bit count of a memory (total number of elements * word
size) must be less than 8 * (1024 * 1024 * 1024 - 2) or 8,573,157,376.
Using Sparse Memory Models
If you design contains a large memory, the simv executable will need
large amounts of machine memory to simulate it. However, if your
simulation only accesses a small number of elements in the design’s
memory, you can use a sparse memory model to significantly reduce
the amount of machine memory that VCS will need to simulate your
design.
You use the /*sparse*/ pragma or metacomment in the memory
declaration to specify a sparse memory model. For example:
reg /*sparse*/ [31:0] pattern [0:10_000_000];
integer i, j;
initial
begin
for (j=1; j<10_000; j=j+1)
for (i=0; i<10_000_000; i=i+1_000)
pattern[i] = i+j;
end
endmodule