User guide

23-36
SystemVerilog Assertion Constructs
Compile-Time And Runtime Options
VCS has the following compile-time option for controllong
SystemVerilog assertions:
-assert keyword_argument
The keyword arguments are as follows:
enable_diag
Enables further control of results reporting with runtime options.
filter_past
For assertions that are defined with the $past system task, ignore
these assertions when the past history buffer is empty. For
instance, at the very beginning of the simulation the past history
buffer is empty. So the first sampling point and subsequent
sampling points should be ignored until the past buffer has been
filled with respect to the sampling point. Using this keyword filters
out vacuous successes too.
disable
Disables all SystemVerilog assertions in the design.
disable_cover
When you include the -cm assert compile-time and runtime
option, VCS include information about cover statements in the
assertion coverage reports. This keyword prevents cover
statements from appearing in these reports.
disable_file=filename
Disables the SystemVerilog assertions specified in the file. See
"Disabling SystemVerilog Assertions at Compile-Time" on page
23-42.