User guide

23-32
SystemVerilog Assertion Constructs
bind dev dev_check #(10) dc1 (clk,sig1,sig2);
Notice that module dev_check, that contains the SVA code, also has
a parameter for specifying the number of clock ticks in the property.
In the parameter declaration it has a value of 5, but its value is
changed to 10 in the bind directive, like in any other module
instantiation.
The VPI For SVA
This VPI is to enable you to write applications that react to SVA events
and to enable you to write SVA waveform, coverage, and debugging
tools.
Note:
To use this API you need to include the sv_vpi_user.h file along
with the vpi_user.h file in the $VCS_HOME/include directory. See
section 28 of the SystemVerilog 3.1a LRM.
This section describes the differences between the VCS
implementation and section 28 of SystemVerilog 3.1a LRM.
• In subsection 28.3.2.2 “Extending vpi_get() and vpi_get_str,” use
vpiDefFileName instead of vpiFileName.
• In subsection 28.4.1 “Placing assertion system callbacks,”
cbAssertionSysStop is not supported.
• In subsection 28.4.2 “Placing assertion callbacks,” the failEpr
step information is not supported.