User guide

23-31
SystemVerilog Assertion Constructs
property p1;
@(posedge clk) a ##1 b;
endproperty
a1: assert property(p1) else $display("p1 Failed");
endmodule
bind top.d1 dev_checker dc1 (clk,a,b);
In this bind directive top.d1 is an instance of module dev.
IMPORTANT:
Binding to an instance that is generated using a generate
statement is not supported.
Parameter Passing In A bind Directive
The module containing the SVA code that is bound to the design
module is instantiated in the bind directive and as such you can use
parameter passing in the instantiation. The following is an example:
`timescale 1ns/1ns
module dev;
logic clk,sig1,sig2;
.
.
.
endmodule
module dev_check(input logic CLOCK,input logic SIG1, input
logic SIG2);
parameter ticks =5;
property p1;
@(posedge CLOCK) SIG1 ##ticks SIG2;
endproperty
a1: assert property(p1) else $display("\n\np1 failed\n\n");
endmodule