User guide

23-30
SystemVerilog Assertion Constructs
a1: assert property(p1) else $display("p1 Failed");
endmodule
bind dev dev_checker dc1 (clk,a,b);
In this bind directive:
bind
Keyword that starts the bind directive
dev
Module identifier (name) of the module to which you want to bind
the SVA module
dev_checker
Module identifier of the SVA module
dc1
Instance name of the SVA module.
(clk,a,b)
Port connection list to the SVA module
You can also bind an SVA module to a design module instances. For
example:
module top;
logic clk,a,b;
.
.
.
dev d1 (clk,a,b);
endmodule
module dev (input logic clk, input logic a, input logic b);
.
.
.
endmodule
module dev_checker (input logic clk, input logic a, input
logic b);