User guide

2-24
Modeling Your Design
Case Statement Behavior
The IEEE Std 1364-2001 standards for the Verilog language state
that you can enter the question mark character (?) in place of the z
character in casex and casez statements. The standard does not
specify that you can also make this substitution in case statements
and you might infer that this substitution is not allowed in case
statements.
VCS, like other Verilog simulators, does not make this inference, and
allows you to also substitute ? for z in case statements. If you do,
remember that z does not stand for "don’t care" in a case statement,
like it does in a casez or casex statement. In a case statement z
stands for the usual high impedance and therefore so does ?.
the power operator:
r1=r2**r3;
yes
attributes:
(* optimize_power=1 *)
module dev (res,out,clk,data1,data2);
yes
generate statements
yes
localparam declarations
yes
Automatic tasks and functions
task automatic t1();
requires the
-sverilog
compile-time
option
constant functions
localparam lp1 = const_func(p1);
yes
parameters with a bit range
parameter bit [7:0][31:0] P =
{32'd1,32'd2,32'd3,32'd4,32'd5,32'd6,32'd7,32'd8};
requires the
-sverilog
compile-time
option
Std 1364-2001 Construct Require +v2k