User guide

23-29
SystemVerilog Assertion Constructs
end
else
begin
$display("p1 does not succeed");
failCount ++;
end
c1: cover property (p1)
begin
$display("p1 covered");
coverCount ++;
end
Binding An SVA Module To A Design Module
You can define a module that contains just SVA sequence and
property declarations, and assert and cover statements. The
module ports are signals in these declarations and statements. These
ports are also signals in a design module (a module that contains
behavioral or RTL code or other types of design constructs).
You can then bind the SVA module to the design module and it is the
same as instantiating the SVA module in the design module. The
following is an example of a design module, and SVA module and a
bind directive that binds the SVA module to the design module:
module dev;
logic clk,a,b;
.
.
.
endmodule
module dev_checker (input logic CLK, input logic A,
input logic B);
property p1;
@(posedge CLK) A ##1 B;
endproperty