User guide

23-28
SystemVerilog Assertion Constructs
- In those nine attempts there were 21 times that the sequence
occurred.
- There were no vacuous matches because the cover statement
does not instantiate a property with an implication.
You can declare a cover statement, in the following places in your
code:
• In a module definition
• In an Interface definition
•In $root
Note:
In the VCS implementation, you can declare a cover statement
in a module definition including inside an always block but not
in an initial block. The Accellera SystemVerilog LRM allows
cover statements in initial blocks.
cover statements, unlike assert statements, only have a pass
action block, not a fail action block, in the VCS implementation.
Action Blocks
assert statements can have a pass and a fail action block, and
cover statements can have a pass action block. The pass block
executes when the assert or cover statement succeeds. The fail
block, that follows the keyword else, executes when the assert
statement fails. The following are examples of these blocks:
a1: assert property (p1)
begin
$display("p1 succeeds");
passCount ++;