User guide

23-27
SystemVerilog Assertion Constructs
VCS, for example, displays the following after simulation as a result
of these cover statements:
"exp3.v", 31: test.c1, 9 attempts, 16 total match, 7 first match, 1 vacuous match
"exp3.v", 32: test.c2, 9 attempts, 21 total match, 8 first match, 0 vacuous match
This display is explained as follows:
• In the first line:
- The cover statement is in source file exp3.v.
- The instance of the cover statement is test.c1. It is declared
in module test.
- There were nine attempts to cover the property p1.
- In those nine attempts there were 16 times that the properly
was true. There can be more than one match in a attempt. In
this case in property p1, in sequence s2, a match can occur
over a range of clock ticks and in this case more than once in
the range.
- There were seven first matches. The property was true seven
times at the start of the range.
- There was a vacuous match. Property p1 contains and
implication. The antecedent sig1 && sig2 was false making
the implication vacuously true because it doesn’t mean that the
consequent sequence s2 occurred.
• In the second line:
- The cover statement is in source file exp3.v.
- The instance of the cover statement is test.c2. It is declared
in module test.
- There were nine attempts to cover the sequence s1.