User guide

23-26

SystemVerilog Assertion Constructs

In this cover statement:

c1:

Instance name of the cover statement. cover statements have

hierarchical name beginning with the hierarchical name of the

module instance in which they are declared, and ending with this

instance name. Instance names are optional.

cover

Keyword for declaring a cover statement.

property

Keyword for instantiating both a property or a sequence.

Property instantiated in the cover statement. You could have

specified a sequence instead of a property.

The following SVA code contains two cover statements:

sequence s1;

@(posedge clk) sig1 ##[1:3] sig2;

endsequence

sequence s2;

sig3 ##[1:3] sig4;

endsequence

property p1;

@(posedge clk) sig1 && sig2 |=> s2;

endproperty

a1: assert property (p1);

a2: assert property (@(posedge clk)s1);

c1: cover property (p1);

c2: cover property (@(posedge clk)s1);

endmodule