User guide

23-25
SystemVerilog Assertion Constructs
Like an asserted property, VCS checks an assumed property and
reports if the assumed property fails to hold.
assume statements are syntactically similar to assert statements, as
stated in the Accellera document. The biasing feature is only useful
when properties are considered as assumptions to drive random
simulation. When a property with biasing is used in an assertion or
coverage, the list operator is equivalent to inside operator, and the
weight specification is ignored. Therefore the following assume
statement is functionally equivalent to the following assert
statement:
a1:assume property @(posedge clk) req dist {0:=40, 1:=60} ;
a1_assertion:assert property req inside {0, 1} ;
cover Statements
The cover statement calls for the monitoring of a property or a
sequence. VCS looks for matches, how often the property was true
or how often the sequence occurred. When simulation is over, VCS
displays the results of this monitoring.
A cover statement is syntactically similar to an assert statement.
The following is an example of a cover statement:
c1: cover property (p1);