User guide

23-24
SystemVerilog Assertion Constructs
property
Keyword for instantiating both a property or a sequence.
p1
Property instantiated in the concurrent assertion. You could also
have specified a sequence instead of a property.
You can declare a concurrent assertion, and enter an assert
statement, in the following places in your code:
• In a module definition
• In an Interface definition
•In $root
Note:
- In the VCS implementation, you can declare a concurrent
assertion in a module definition including inside an always
block but not in an initial block. The Accellera
SystemVerilog LRM allows concurrent assertions in initial
blocks.
If a property has formal arguments you can replace them with other
signals as shown in "Using Formal Arguments in a Property" on page
23-18.
assume Statements
The assume statement specifies a property that VCS can assume
about the simulation environment. As specified in the Accellera
language reference manual, an assume statement is a hypothesis
for proving asserted properties in assert statements.