User guide

23-23
SystemVerilog Assertion Constructs
sig1 ##1 sig2;
endsequence
property p1;
@(posedge clk) disable iff (rst) s1;
endproperty
a1: assert property (p1);
If during simulation sig2 turns false, the property no longer succeeds.
If, some time later, rst turns true, the property starts to succeed again.
If rst turns false again, the property once again no longer succeeds.
assert Statements
VCS never checks a property or a sequence unless it is instantiated
in a concurrent assertion. The concurrent assertion enforces the
property or sequence as a checker of that property or sequence.
A concurrent assertion takes the form of an assert statement. The
following is an example of an assert statement:
a1: assert property (p1);
In this assert statement:
a1:
The instance name of the concurrent assertion. Concurrent
assertions have hierarchical name beginning with the hierarchical
name of the module instance in which they are declared, and
ending with this instance name. Instance names are optional.
assert
Keyword for declaring a concurrent assertion.