User guide

23-22
SystemVerilog Assertion Constructs
Past Value Function
SystemVerilog has a $past system function that returns the value
of a signal from a previous clock tick. The following is an example of
its use:
property p1;
@(posedge clk) (cnt == 0) ##3 ($past(cnt,3)==0);
endproperty
This rather elementary use of the $past system function returns the
value of signal cnt from three clock ticks ago. The first argument, an
expression, is required. The second argument, a number of clock
ticks previous to the current clock tick, is optional and defaults to 1.
The disable iff Construct
The disable iff construct enables the use of asynchronous resets.
It specifies a reset condition in which all attempts that have started
for properties immediately succeed, and all subsequent attempts
succeed as soon as they start.
The following shows a use of the disable iff construct:
initial
begin
clk=0;
rst=0;
sig1=1;
#7 sig2=1;
.
.
.
end
always
#5 clk=~clk;
sequence s1;