User guide

23-17
SystemVerilog Assertion Constructs
case condition s1.triggered happened
do while condition s1.triggered
Properties
A property says something about the design, so a property evaluates
to true or false.
Concurrent assertions use properties and properties contain
sequences, either instantiated or containing sequential expressions
like a sequence. Both of the following sequences and all but the last
of the following properties are valid:
sequence s1;
sig1 ##1 sig2;
endsequence
sequence s2;
@(posedge clk) sig3 ##1 sig4;
endsequence
property p1;
@(posedge clk) s1;
endproperty
property p2;
@(posedge clk) s2;
endproperty
property p3;
@(posedge clk2) sig1 ##1 sig2;
endproperty
property p4;
@(posedge clk2) s2; //illegal
endproperty