User guide

23-16
SystemVerilog Assertion Constructs
always @(s1)
$display("sequence s1 event control at %0t\n",$time);
Sequence s1 is an event control expression.
initial
begin
wait (s1.triggered)
$display("wait condition s1.triggered\n");
The triggered method with sequence s1 is the conditional
expression for the wait statement.
if (s1.triggered)
$display("if condition s1.triggered\n");
case (s1.triggered)
1'b1 : $display("case condition s1.triggered happened\n");
1'b0 : $display("s1.triggered did not happen\n");
endcase
do
begin
$display("do while condition s1.triggered\n");
$finish;
end
while (s1.triggered);
end
endmodule
The triggered method with sequence s1 is also the conditional
expression for the if, case, and do while statements.
Sequence s1 does occur, so VCS displays the following:
sequence s1 event control at 15
wait condition s1.triggered
if condition s1.triggered